The present disclosure relates to circuit simulation methods and semiconductor integrated circuits designed by the circuit simulation methods, and more particularly to highly accurate circuit simulation methods in view of a change in the electrical characteristics of transistors caused by the influence of the layout patterns of metal films and insulating films, which are deposited during manufacturing processes, and semiconductor integrated circuits designed by the methods.
In recent years, a further improvement in simulation accuracy of circuit simulators has been demanded in development in system LSIs etc. As miniaturization in semiconductor processes proceeds, the layout patterns and the layout of circuit elements have largely influenced the performance of semiconductor integrated circuits.
In particular, heat distribution of a wafer substrate varies during heat treatment depending on the area ratios and the forms of metal films and insulating films, which are deposited during a manufacturing process. Accordingly, the threshold voltages of transistors could vary. For example, I. Ahsan et al., RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65 nm Technology, Symp. on VLSI Technology, pp. 170-171, 2006 reports that a wafer temperature during heat treatment changes according to, for example, the area ratio of an isolation region around a transistor thereby changing delay in the transistor.
As such, the electrical characteristics of a transistor could largely change depending on mask layout patterns forming a metal film and an insulating film. In particular, numbers of transistors in pairs, which require relatively small characteristic differences, are used in a differential amplifier circuit, a current mirror circuit, etc. Thus, a change in the characteristics caused by the layout pattern could influence the performance, the yields, etc. of the circuit. Therefore, the change in the characteristics caused by the layout pattern needs to be highly accurately estimated at a design stage.
Japanese Patent Publication No. 2008-85030 suggests a highly accurate circuit simulation method. In the method, the form of an active region around a transistor (e.g., the width of an isolation region, the length of an active region adjacent to the transistor with the isolation region interposed therebetween, etc.) is defined as a form parameter of the deformation of the transistor to execute the circuit simulation in view of a change in the deformation according to mechanical stress caused by a layout pattern. A mathematical model including the form parameters representing the electrical characteristics of the transistor is used to carry out the simulation method.
FIG. 17 is a top view of a circuit to be simulated and illustrates a parameter used in a mathematical model representing the electrical characteristics of a transistor in a conventional circuit simulation method.
In the figure, a transistor 25 surrounded by an isolation region is formed on a semiconductor substrate. Adjacent active regions 26 are formed around the transistor 25 with the isolation region interposed therebetween. Mechanical stress is caused in a channel region of the transistor 25 by a difference in the coefficient of thermal expansion between the isolation region and the active regions, thereby changing the electrical characteristics of the transistor.
In the conventional method, in order to consider a change in the characteristics caused by the layout patterns of the adjacent active regions 26, a length 27 between the end of the active region of the transistor 25 and the end of each of the facing active region 26, and a length 28 of the adjacent active region 26 are defined as parameters, and used in an approximation expression representing the electrical characteristics.
The mechanical stress reaches its peak at the boundary between the isolation region and the active region, and the distance between the boundary and the transistor determines the influence of the mechanical stress. Thus, as shown in the conventional method, the length parameters 27 and 28 accurately express a change in the electrical characteristics.
However, the layout pattern of a metal film deposited during the manufacturing process of the transistor, and the layout patterns of the active region and a gate electrode could cause variations in substrate temperature distribution during heat treatment, thereby changing the electrical characteristics such as the threshold voltage of the transistor. In this phenomenon, not only the distance between the layout pattern and the transistor but also the area ratio of the layout pattern influence a change in the electrical characteristics.
As described above, in the conventional method, sufficiently accurate circuit simulation cannot be provided simply by defining and considering only the distance parameters such as the length 27 between the adjacent active region and the transistor, and the length 28 of the adjacent active region. Then, the performance and the yields of the circuit may be deteriorated.
It is an objective of the present disclosure to solve the problems of the conventional method, and to provide a circuit simulation method with a small simulation error, and a semiconductor integrated circuit, which estimates a change in electrical characteristics caused by a layout pattern at the design stage, and reduces deterioration in the performance and the yields of the circuit.